【加照片】
莎拉 L. 哈里斯（Sarah L. Harris） 内华达大学电子与计算机工程系副教授，拥有斯坦福大学电子工程博士学位。她曾在惠普、圣地亚哥超算中心、英伟达公司和微软亚洲研究院工作，擅长计算机体系结构设计和系统设计。
戴维莫尼哈里斯（David Money Harris） 哈维玛德学院工程系教授，拥有斯坦福大学电子工程博士学位。他曾在英特尔公司从事Itanium和Pentium II处理器的逻辑和电路设计，并曾担任Sun Microsystems、惠普、Evans & Sutherland等设计公司的顾问，获得了12项专利。
目錄：
Contents
Preface . vi
Features . vii
Online Supplementsviii
How to Use the Software Tools in a Courseix
Labsix
Bugsx
Acknowledgmentsxi
Chapter 1 From Zero to One3
1.1 TheGamePlan 3
1.2 The Art of Managing Complexity . 4
1.2.1 Abstraction4
1.2.2 Discipline5
1.2.3 The Three-Ys6
1.3 The Digital Abstraction7
1.4 Number Systems. 9
1.4.1 Decimal Numbers9
1.4.2 Binary Numbers9
1.4.3 Hexadecimal Numbers . 11
1.4.4 Bytes, Nibbles, and All That Jazz . 13
1.4.5 Binary Addition . 14
1.4.6 Signed Binary Numbers15
1.5 Logic Gates19
1.5.1 NOT Gate20
1.5.2 Buffer20
1.5.3 AND Gate20
1.5.4 OR Gate . 21
1.5.5 Other Two-Input Gates21
1.5.6 Multiple-Input Gates . 21
1.6 Beneath the Digital Abstraction22
1.6.1 Supply Voltage22
1.6.2 Logic Levels22
1.6.3 Noise Margins23
1.6.4 DC Transfer Characteristics24
1.6.5 The Static Discipline . 24
1.7 CMOSTransistors 26
1.7.1 Semiconductors27
1.7.2 Diodes27
1.7.3 Capacitors28
1.7.4 nMOS and pMOS Transistors28
1.7.5 CMOS NOT Gate . 31
1.7.6 Other CMOS Logic Gates . 31
1.7.7 Transmission Gates33
1.7.8 Pseudo-nMOS Logic . 33
1.8 Power Consumption34
1.9 Summary and a Look Ahead35
Exercises37
Interview Questions . 52
Chapter 2 Combinational Logic Design55
2.1 Introduction 55
2.2 BooleanEquations 58
2.2.1 Terminology58
2.2.2 Sum-of-Products Form . 58
2.2.3 Product-of-Sums Form . 60
2.3 BooleanAlgebra 60
2.3.1 Axioms . 61
2.3.2 Theorems of One Variable . 61
2.3.3 Theorems of Several Variables62
2.3.4 The Truth Behind It All64
2.3.5 Simplifying Equations65
2.4 From Logic to Gates66
2.5 Multilevel Combinational Logic 69
2.5.1 Hardware Reduction . 70
2.5.2 Bubble Pushing71
2.6 Xs and Zs, Oh My73
2.6.1 Illegal Value： X . 73
2.6.2 Floating Value： Z74
2.7 Karnaugh Maps75
2.7.1 Circular Thinking . 76
2.7.2 Logic Minimization with K-Maps . 77
2.7.3 Don''t Cares . 81
2.7.4 The Big Picture82
2.8 Combinational Building Blocks83
2.8.1 Multiplexers . 83
2.8.2 Decoders . 86
2.9 Timing. 88
2.9.1 Propagation and Contamination Delay88
2.9.2 Glitches . 92
2.10 Summary95
Exercises97
Interview Questions106
Chapter 3 Sequential Logic Design109
3.1 Introduction. 109
3.2 Latches and Flip-Flops . 109
3.2.1 SR Latch . 111
3.2.2 D Latch113
3.2.3 D FIip-Flop . 114
3.2.4 Register . 114
3.2.5 Enabled Flip-Flop . 115
3.2.6 Resettable Flip-Flop116
3.2.7 Transistor-Level Latch and Flip-Flop Designs116
3.2.8 Putting It All Together . 118
3.3 Synchronous Logic Design 119
3.3.1 Some Problematic Circuits119
3.3.2 Synchronous Sequential Circuits120
3.3.3 Synchronous and Asynchronous Circuits . 122
3.4 Finite State Machines123
3.4.1 FSM Design Example123
3.4.2 State Encodings . 129
3.4.3 Moore and Mealy Machines132
3.4.4 Factoring State Machines . 134
3.4.5 Deriving an FSM from a Schematic . 137
3.4.6 FSM Review140
3.5 Timing of Sequential Logic . 141
3.5.1 The Dynamic Discipline142
3.5.2 System Timing142
3.5.3 Clock Skew . 148
3.5.4 Metastability151
3.5.5 Synchronizers . 152
3.5.6 Derivation of Resolution Time154
3.6 Parallelism157
3.7 Summary . 161
Exercises162
Interview Questions171
Chapter 4 Hardware Description Languages173
4.1 Introduction. 173
4.1.1 Modules173
4.1.2 Language Origins . 174
4.1.3 Simulation and Synthesis . 175
4.2 Combinational Logic. 177
4.2.1 Bitwise Operators . 177
4.2.2 Comments and White Space180
4.2.3 Reduction Operators . 180
4.2.4 Conditional Assignment181
4.2.5 Internal Variables . 182
4.2.6 Precedence184
4.2.7 Numbers185
4.2.8 Zs and Xs . 186
4.2.9 Bit Swizzling188
4.2.10 Delays188
4.3 Structural Modeling 190
4.4 Sequential Logic . 193
4.4.1 Registers193
4.4.2 Resettable Registers194
4.4.3 Enabled Registers196
4.4.4 Multiple Registers . 197
4.4.5 Latches . 198
4.5 MoreCombinationalLogic. 198
4.5.1 Case Statements . 201
4.5.2 If Statements202
4.5.3 Truth Tables with Dont Cares . 205
4.5.4 Blocking and Nonblocking Assi
內容試閱：
PrefaceThis book is unique in its treatment in that it presents digital logic design from the perspective of computer architecture, starting at the beginning with 1s and 0s, and leading through the design of a microprocessor.We believe that building a microprocessor is a special rite of passage for engineering and computer science students. The inner workings of a proces-sor seem almost magical to the uninitiated, yet prove to be straightforward when carefully explained. Digital design in itself is a powerful and exciting subject. Assembly language programming unveils the inner language spoken by the processor. Microarchitecture is the link that brings it all together.The first two editions of this increasingly popular text have covered the MIPS architecture in the tradition of the widely used architecture books by Patterson and Hennessy. As one of the original Reduced Instruction Set Computing architectures, MIPS is clean and exceptionally easy to understand and build. MIPS remains an important architecture and has been infused with new energy after Imagination Technologies acquired it in 2013.Over the past two decades, the ARM architecture has exploded in popularity because of its efficiency and rich ecosystem. More than 50 bil-lion ARM processors have been shipped, and more than 75% of humans on the planet use products with ARM processors. At the time of this writ-ing, nearly every cell phone and tablet sold contains one or more ARM processors. Forecasts predict tens of billions more ARM processors soon controlling the Internet of Things. Many companies are building high-per-formance ARM systems to challenge Intel in the server market. Because of the commercial importance and student interest, we have developed this ARM edition of this book.Pedagogically, the learning objectives of the MIPS and ARM editions are identical. The ARM architecture has a number of features including addressing modes and conditional execution that contribute to its effi-ciency but add a small amount of complexity. The microarchitectures also are very similar, with conditional execution and the program counter being the largest changes. The chapter on IO provides numerous exam-ples using the Raspberry Pi, a very popular ARM-based embedded Linux single board computer.We expect to offer both MIPS and ARM editions as long as the mar-ket demands.FEATURESSide-by-Side Coverage of SystemVerilog and VHDLHardware description languages HDLs are at the center of modern digi-tal design practices. Unfortunately, designers are evenly split between the two dominant languages, SystemVerilog and VHDL. This book intro-duces HDLs in Chapter 4 as soon as combinational and sequential logic design has been covered. HDLs are then used in Chapters 5 and 7 to design larger building blocks and entire processors. Nevertheless, Chapter 4 can be skipped and the later chapters are still accessible for courses that choose not to cover HDLs.This book is unique in its side-by-side presentation of SystemVerilog and VHDL, enabling the reader to learn the two languages. Chapter 4 describes principles that apply to both HDLs, and then provides language-specific syntax and examples in adjacent columns. This side-by-side treatment makes it easy for an instructor to choose either HDL, and for the reader to transition from one to the other, either in a class or in professional practice.ARM Architecture and MicroarchitectureChapters 6 and 7 offer the first in-depth coverage of the ARM architec-ture and microarchitecture. ARM is an ideal architecture because it is a real architecture shipped in millions of products yearly, yet it is stream-lined and easy to learn. Moreover, because of its popularity in the com-mercial and hobbyist worlds, simulation and development tools exist for the ARM architecture. All material relating to ARM. technology has been reproduced with permission from ARM Limited.Real-World PerspectivesIn addition to the real-world perspective in discussing the ARM architec-ture, Chapter 6 illustrates the architecture of Intel x86 processors to offer another per
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